The 3D package technology with TSV (through-silicon-via) have been quickly proliferating in diverse fields of applications as a practical more-than-Moore solution of upcoming decades. Mass production has already been started in the form of same die stacking such as DDR Memory and HBM (High Bandwidth Memory). Recently, since many companies with high-end technologies are interested in chiplets, heterogeneous 2.5D/3D chip integrations are expected to be applied more and more and the technical requirements for packages should be improved to meet the increase of interconnect density and the decrease of interconnect length between chiplets.
Definitely, heterogeneous 2.5D/3D chip integration is a comprehensive task requiring innovative changes in all areas including IC design, fabrication processes, thermal management, and characterization. Therefore, close collaboration among industry, universities, and research institutes is crucial to resolve those problems. The organizers of the workshop have invited leading experts from diverse sites to share their expertise and experiences with others who need guidance and advice.
You are cordially invited to the forum of informative lecture and open discussion with world-best leaders in 2.5D/3D packaging technology.
Joong Hwee Cho (President, Semiconductor Society, IEIE)
Jinsang Kim (Workshop Organizer)
Byoung Hun Lee (Workshop Organizer)
Unbyoung Kang (Workshop Organizer)
Changhwan Choi (Workshop Organizer)
Advanced packaging technology workshop
DATE
2021.09.24 (Friday)
VENUE
On-line
WEBSITE
http://aptw2021.ieieweb.org
위원장 : 이병훈 교수(포항공과대학교)
위 원 : 김진상 교수(경희대학교), 강운병 마스터(삼성전자), 최창환 교수(한양대학교)
TOPIC/CHAIR/SPEAKER
08:30~08:55
REGISTERATION
08:55~09:10
OPENING, Joong Hwee Cho, Incheon University
SESSION-1
Session chair: Byoung Hun Lee, CSTC, POSTECH
09:10~10:00
Advanced Package Trends
S.C.Song, Qualcomm
10:00~10:50
Design technology for advanced package
Sung-Kyu Lim, Geogia Institute of technology
10:50~11:40
Cu Technology in Advanced Packaging: Past, present and the future
Jinho An, AMAT
Process technology for advanced package
김사라은경 (서울과기대)
13:50~14:40
Advanced Package FAB Solutions for Next Generation Devices
Seung Wook Yoon, Ph.D, MBA, Samsung Electronics
14:40~15:10
COFFEE BREAK
SESSION-3
Session chair: Changhwan Choi, Hanyang University
15:10~16:00
System 3D-IC LVS&DRC with Advanced Package Design
이근환 Principle application engineer, Cadence
16:00~16:50
2.5D/3D 고집적 패키지 기술 동향
강인수소장 (Nepes)
16:50~17:00
CLOSING
Advanced Package Trends S.C.Song, Qualcomm
Partition of monolithic 2D (M2D) chip and Heterogeneous Integration (HI) of resultant chiplets are inevitable in the near future due to the rising cost of transistor and the ever-increasing complexity of process. 3D stacking is required to maintain tight cross-IP communication and fit into the limited footprint over Printed Circuit Board (PCB). This new paradigm change in system-level technology requires the build-up of appropriate industry eco-system to be cost-effective for long-term sustainable growth. We'll discuss the technical and business aspects of HI and 3DIC.
3D ICs: Benefits, Challenges, and Future Prospects Sung-Kyu Lim, Geogia Institute of technology
3D IC는 package 되지 않은 bare die들을 적층하고 연결하는 기술입니다. 적층 방식에 따라 (1) micro-bump 3D (20-50um pitch), (2) bump 없이 copper pad를 직접 연결하는 hybrid bonding 3D (1-20um pitch), 그리고 (3) 순차적으로 아래층에서 위로 한층 씩 쌓아가는 monolithic 3D (0.1um – 1um pitch) 등이 있습니다. 3D IC는 transistor의 scaling이 멈추어도 transistor의 숫자를 계속 증가시키는 가장 효과적인 (혹은 유일한) 방법으로 인정 받고 있습니다. 또한, 수율과 비용, 그리고 power, performance, area (PPA) 측면에서도 one node 이상의 개선 효과를 보이는 연구들이 발표되어 있습니다. 이번 세미나에서 GTCAD (Georgia Tech Computer-aided Design) 연구소에서 20여년간 진행한 3D IC 아키텍처, 회로 설계, 및 EDA 툴 개발 관련 연구 내용과 성과를 요약해서 발표하겠습니다.
Cu Technology in Advanced Packaging: Past, present and the future Jinho An, AMAT
The introduction of Cu in the late 80s was a monumental moment for the semiconductor industry. The dry etch limitations of Cu brought the need to implement a completely new integration flow, which was only possible thanks to the development of barrier metal/seed, Cu electroplating, chemical mechanical polishing, and other new processes. This presentation will look at how Cu reshaped the interconnect technology, and see how it has affected today’s advanced packaging technology in the form of through silicon vias and redistribution layers. These new design elements are actively addressing the power and performance needs that have hampered the front end technology as the Moore’s law comes to a close. Moving forward, the presentation will discuss the challenges ahead as the industry looks to die-to-wafer hybrid bonding and power distribution networks as solutions to future semiconductor technology hurdles.
Process technology for advanced package 김사라은경 (서울과기대)
반도체 기술은 ITRS에 의거하여 소자 스케일링으로 발전해 왔고, 많은 기능이 통합된 SOC 방법이 활발하게 개발되어 왔다. 그러나, 최근 소자 스케일링의 물리적 한계 시점에서 FOWLP(fan-out wafer level packaging), 3D packaging, chiplet 등 다양한 첨단반도체패키징 기술이 각광을 받고 있다. 특히, TSMC와 인텔의 경우 InFoWLP, CoWoS, EMIB, Foveros, ODI 등 HI(heterogeneous integration) 구조를 적극적으로 소개하고 있으며, 미래 반도체 기술은 첨단반도체패키징 기술로 빠르게 패러다임이 변화하고 있다. 본 세미나에서는 변화하고 있는 HI의 개념, 방향, 그리고 첨단반도체패키징 제조기술을 소개할 예정이다.
Advanced Package FAB Solutions for Next Generation Devices Seung Wook Yoon, Ph.D, MBA, Samsung Electronics
SAMSUNG Advanced Package FAB solutions provide complementary and extended solutions with complete supply chain management including Fanout WLP, Panel level PKG, 2.5D as well as 3D Integration. In this presentation, the advanced package FAB solutions are to be introduced and discussed in terms of challenges and opportunities for emerging high-end computing and mobile device platforms. Furthermore, Fanout WLP, RDL interposer, high-performance 3D SIP and Integrated Stacked Capacitor (ISC) are introduced.
System 3D-IC LVS&DRC with Advanced Package Design 이근환, Principle application engineer, Cadence
Samsung Foundry와 MDI(Multi Die Integration-2.5D/3D) 관련 진행 되었던 내용중, 3D-IC 및BGA PKG(Advanced Package Designed)를 이용한 System LVS/DRC의 New Workflow와 Allegro Package Design Tool인 Silicon Option을 이용한 Advanced Package Design 내용을 소개합니다.
2.5D/3D 고집적 패키지 기술 동향 강인수 소장 (Nepes)
반도체 후공정 기술에서 최근에 고집적 패키지 SiP(System in Package)에 대한 수요가 크게 증가하고 있습니다. 5G Mobile Networking 및 인공지능(AI) 시대 진입에 따라 데이터가 폭증하면서 데이터를 소화할 수 있는 반도체 성능이 요구되면서 반도체 미세화를 넘어 2.5D 및 3D 적층 기술을 활용해 이종의 칩들을 집적화 하는 고집적 패키징 기술개발에 속도를 높이고 있는 상황입니다. 고집적 패키징 트렌드 및 다양한 고집적 패키지 기술들에 대해 소개하고자 합니다.
